Random-access memory (RAM) is a critical element that determines the speed, performance and capabilities of any computing platform. As a re¬sult, memory technologies continue to evolve at a rapid rate. However, that is not sufficient - the in¬terfaces of these RAM devices must also evolve to keep pace, so that these memory devices can be utilised easily and com¬pletely by various computing systems. And we must say that the interfaces are keeping pace with the memory technologies. Version 3 of the double-date¬rate synchronous dynamic random-access memory (DDR3 SDRAM) in¬terface specifica¬tion is gaining ground, even as its pred~¬cessor DDR2 continues to have a wing of followers.

DDR3 is for high-bandwidth applica¬tions. It has the ability to transfer data at twice the rate of DDR2. This enables higher bus rates, higher peak rates and a larger memory module size. The one disadvantage, however, is that DDR3 is not backward-compatible with DDR2.
Ethernet-capable SDRAM data rates have also doubled approximately every three years to 1.8 gigatransfer/ second (GT/s). At the same time, the power supply voltage has decreased significantly resulting in lower power consumption. As a result, SDRAM sig¬nals are now faster and smaller.

There is a bit of recent activity re¬lated to memory interfaces for mobile devices, which now use the mobile DDR interface technology. The new low-power DDR2 (LPDDR2) mobile interface technology is also catching up. But some vendors feel even that is inadequate for the requirements of the next wave of devices which will most likely use three-dimensional integrated circuits based on through-silicon vias or TSVs! Technologi~s like LPDDR2, despite its 4.3Gbps capability, cannot meet the bandwidth requirements of these devices. Hence players such as the Serial Port Memory Technol¬ogy Consortium (SPMT), the MIPI Alliance that focuses on standards for mobile interfaces and Rambus' XDR are working towards developing new interfaces that would have two to three times more bandwidth than current technologies.

SPMT, for instance, announced a new specification in June that is based on the new 'SeriaISwitch' technology, which reportedly delivers four times the bandwidth, pin for pin, at half the power of existing memory solu¬tions, and offers a low-cost migration from parallel to serial memories. It is backward-compatible with exist¬ing LPDDR2, and operates in legacy LPDDR2 mode with up to 1.6 Gbps in parallel mode. It is said to switch into overdrive in serial mode with up to 6.4 Gbps of bandwidth per channel.